Currently we have an update from Intel about its details middle and AI enterprise. We have been pre-briefed on the update but will be covering the party reside. Hope to hear a lot more about Intel Xeon roadmap updates as nicely as new technologies, including the MCR DIMM or Multiplexer Mixed Ranks DIMM that we lined not too long ago.
Be aware, this is currently being protected reside so remember to justification typos.
Intel DCAI 2023 Update New Technologies and Up-to-date Xeon Roadmap
A massive element of today’s function is focused on the trader community, so there is a big part of this that is on the TAM for DCAI or marketplace opportunity.
Intel mentioned that it is likely to improve cores for each socket and so it expects its main progress to comply with field tendencies even if sockets development is diverse.
Intel says it is going to speed up its main density faster than it had been. In this article is the Updated AMD EPYC and Intel Xeon Main Counts About Time check out that we shared before this 12 months.
Intel reported it plans to raise ASP to seize the benefit of getting more cores. It will also seize the worth from other portfolio IP.
Intel says that the market place has developed to assistance the two higher-performance cores as very well as lessen-effectiveness dense cores.
Intel is talking about P-main “Rapids” merchandise and E-main “Forest” chips.
Intel claims it strategies to re-use I/O chiplets and memory controllers between Rapids and Forest products and solutions. Intel would seem to be subsequent AMD EPYC’s IO Die-like models.
Intel states that it has 450+ 4th Gen Intel Xeon Scalable “Sapphire Rapids” types, but fewer than fifty percent of these are at present in the marketplace. Intel suggests that the crossover for SPR quantity will occur mid-year. It also hopes when China comes back and when enterprises get started shelling out less cautiously that it will support raise income.
Intel is exhibiting a demo working with Intel AMX acceleration to present how its chips can be a lot quicker than AMD EPYC components. You can master much more about that in: Fingers-on Benchmarking with Intel Sapphire Rapids Xeon Accelerators.
Later this year is the Emerald Rapids. Below is that chip. I missed the <5 second clip of the chip close up.
Emerald Rapdis will be the 5th Gen Intel Xeon Scalable series. It is a drop-in replacement for Sapphire Rapids servers. This is different than the Ice Lake generation which was a single-generation platform.
5th Gen Xeon Scalable will be on Intel 7.
Sierra Forest in the first half of 2024. Granite Rapids shortly thereafter. Granite Rapids will be on Intel 3.
Granite Rapids will have MCR DIMMs. Those will offer 1.5TB/s of memory bandwidth in a dual-socket server.
Here is DDR5-8800 running with Intel MLC:
Intel’s Sierra Forest is expected in 1H’24. We usually expect “1H” to mean June based on previous launches. This will be an Intel 3 platform.
Sierra Forest is 144 cores and is booting OSes and running stress-ng.
Clearwater Forest in Intel 18A in 2025. This is the next E-core design.
Here is the Xeon roadmap between now and 2025.
Here is the DCAI Roadmap including other products. I asked about the lack of HBM accelerators. Intel told me that they will be addressing higher performance memory updates in the future.
Something to note here is that the GPU, Habana Gaudi AI accelerator and FPGAs are continuing. 15 new FPGAs in 2023 is a lot.
Here is Intel’s AI Accelerator TAM:
Intel is talking about OneAPI and SYCL. The pace of this is fast enough that we are going to leave most of that for others since there is not as much being announced here and seems like it is more of a recap.
More to come as the event progresses.
There is a lot in here. The P-core versus E-core mix is something we are really interested in at STH. Intel gave us a wide range of the expected future mix of P-cores versus E-cores that it could be shipping in a few years. To be frank, I am much more excited about Sierra Forest than Emerald Rapids at this point. As we increase the number of dedicated accelerators in the ecosystem, having E-cores alongside accelerators may make sense. Also, there are many servers simply running nginx serving web pages that do not need optimizations for high-performance computing.
I asked about what the IO Die or Tile will be called. Intel told me that the exact name is not finalized.