Rodrigo Andresen
At the IEDM conference, Intel shared its process technology roadmap and its vision for chip designs that will be available in the next three to four years. As expected, Intel’s next-generation fabrication processes — Intel 4 and Intel 3 — are on track to be used for high-volume manufacturing (HVM) in 2023 and 2024, respectively. Furthermore, the company’s 20A and 18A production nodes will be ready for HVM in 2024, which means that 18A will be made available ahead of schedule, a slide published by IEEE Spectrum (opens in new tab) suggests.
Intel’s Technologies Between Now and 2025
| Node: | Intel 7 | Intel 4 | Intel 3 | Intel 20A | Intel 18A |
|---|---|---|---|---|---|
| Status: | HVM | Ready Now | Ready in H2 2023 | Ready in H1 2024 | Ready in H2 2024 |
| Notable Products: | Raptor Lake, Sapphire Rapids | Meteor Lake | Granite Rapids, Sierra Forest | Arrow Lake | Future Lake, Future Rapids, IFS |
NOTE: Process technology readiness does not mean HVM start.
Intel 4 Ready Today, Intel 3 Due in H2 2023
Next year Intel will release its 14th Generation Core codenamed Meteor Lake CPU, its first mass-market client processor featuring a multi-chiplet (or multi-tile) design with each chiplet set to be made using a different process technology. Intel’s Meteor Lake products will comprise four tiles: the compute tile (CPU cores) made using Intel 4 process technology (aka 7nm EUV), the graphics tile produced by TSMC presumably using its N3 or N5 node, the SoC tile, and the I/O tile. In addition, the tiles will be interconnected using Intel’s Foveros 3D technology.
Meteor Lake’s compute tile is arguably the most exciting part of the package because it will be made on Intel 4 (previously known as 7nm), the company’s first production node that will use extreme ultraviolet (EUV) lithography. This fabrication process is ready for mass production, according to Intel, though it will be deployed for the HVM of Meteor Lake’s compute chiplet only several months from now. Keeping in mind that Intel powered on this compute tile in October 2021, it is not surprising that the node is ready for production by now. What is a bit unexpected is that Intel does not confirm that this process technology is used to make Ponte Vecchio’s Xe-HPC compute GPU tiles, as planted two years ago.
Intel will start using EUV nearly four years after TSMC, which began to produce chips on its N7+ node in Q2 2019. Intel needs to ensure that its 4nm-class node performs up to expectations and delivers good yields, as it will be the first node to arrive after the company’s rather unlucky 10nm family of processes that did not perform as expected early in its lifecycle and which costs are higher than the company hoped several years ago.
Since Intel has to catch up with its rivals Samsung Foundry and TSMC, its Intel 4 process technology will already be joined by its Intel 3 fabrication node (3nm-class) in 2023 ~ 2024. This process will be manufacturing-ready in the second half of 2023, based on data shared by Intel. It will be used to make Intel’s codenamed Granite Rapids and Sierra Forest processors, which are high-profile products for the company. Sierra Forest is expected to be the company’s first data center CPU to use energy-efficient cores and will compete against various Arm-based offerings with high core counts.
Intel already has to work on Xeon ‘Granite Rapids’ samples, so it looks like the design of the CPU is ready, and the node itself is on track for HVM 2024.
“The first stepping of Granite Rapids is out of the fab, yielding well, with Intel 3 continuing to progress on schedule,” said Pat Gelsinger, chief executive of Intel, at the most recent earnings call. “Emerald Rapids is showing good progress and is on track for the complete year 2023, Granite Rapids is very healthy running multiple OSs across many configurations, and with Sierra Forest, our first E-core product providing world-class performance per watt, are both solidly on track for 2024.”
Intel’s 18A Moved in to H2 2024
Playing catch up with TSMC and Samsung is important, but to return its process technology leadership, Intel will have to leapfrog both of its rivals. This is set to happen sometime in 2024 when the company unveils its 20A (20 angstroms, or 2nm) node that will use its gate-all-around transistors branded RibbonFET as well as backside power delivery called PowerVia. Intel expects its 20A node to be manufacturing ready in the first half of 2024; it will be used to make — among other things — chiplets for the company’s codenamed Arrow Lake processors for client PCs in 2024.
Intel’s 20A will be the industry’s first 2nm-class node, and it will also extensively use EUV to maximize transistor density, provide decent performance improvements, and lower power consumption. In 2024, it is set to compete against TSMC’s third-generation 3nm-class (N3S, N3P) process technologies designed for enhanced transistor density and performance. It remains to be seen how these three nodes stack against each other. Still, Intel is setting the bar very high for its 20A process as it simultaneously introduces two major innovations (GAA, BPD).
And yet, 20A is not the most advanced process technology that Intel plans to start using by late 2025. The company is also readying its 18A (18 angstroms, 1.8nm) production node that promises to further increase PPA (performance, power, area) advantages for Intel and its Intel Foundry Services customers.
For 18A, Intel originally planned to use EUV tools with 0.55 numerical aperture (NA) optics, which is set to provide an 8nm resolution (down from 13nm in the case of currently used EUV tools with a 0.33 NA). But ASML’s production of High-NA EUV equipment will only be ready in 2025, whereas Intel targets its 18A to be prepared for manufacturing in the second half of 2025, ahead of its rivals.
Since it is possible to get to an 8nm resolution for post-3nm-nodes with multi-patterning using current-generation EUV tools (though this will lengthen production cycles and could potentially affect yields), Intel is willing to take some additional risks with 18A and use ASML’s Twinscan NXE:3600D or NXE:3800E to make chips on this node as it believes that it will bring it undisputed market leadership.
As it turns out, the first 20A and 18A test chips have been taped out already.
“On Intel 20A and Intel 18A, the first nodes to benefit from RibbonFet and PowerVia, our first internal test chips and those of a major potential foundry customer have taped out with silicon running in the fab,” said the head of Intel. “We continue to be on track to regain transistor performance and power performance leadership by 2025.”
System Technology Co-Optimization
Both 20A and 18A production nodes will extensively use EUV tools (and potentially even High-NA EUV tools), making chips produced on these technologies extremely expensive. Even today’s large monolithic 4nm and 5nm chips are costly to develop, validate, and produce, which is why multi-tile designs like Intel’s Ponte Vecchio are gaining popularity. At 2nm and 1.8nm, it will make sense to disaggregate high-performance designs further.
To do so, Intel believes that an all-new new ‘outside-in’ design approach will be needed. Intel envisions that several years down the road, chip designers will be able to disaggregate functions of a single chip into a multi-chiplet design and then produce chiplets using the most optimal technology to meet their performance, power, and cost goals. Intel calls such approach system technology co-optimization (STCO). For example, since logic scales better than SRAM, it makes sense to produce logic and caches using different nodes (for optimal costs and performance) and then stitch them together using technologies like Foveros or EMIB.
Given such an approach, a successful foundry will have to offer various nodes for different chiplets and competitive packaging technologies. This is why Intel needs to provide the best logic technology (i.e., 20A and 18A) ahead of its rivals to ensure that it makes the most lucrative parts of those upcoming multi-tile designs.
